INFINEON CY7C1441KV33-133AXI SRAM, Synchronous SRAM, 36 Mbit, 1M x 36bit, TQFP, 100 Pins, 3.135 V

CY7C1441KV33-133AXI is a synchronous flow-through SRAM designed to interface with high-speed microprocessors with minimum glue logic. A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock (CLK) input. The device allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the processor address strobe (active-low ADSP) or the cache controller address strobe (active-low ADSC) inputs. Address advancement is controlled by the address advancement (active-low ADV) input. Addresses and chip enables are registered at rising edge of clock when either address strobe processor (active-low ADSP) or address strobe controller active-low (ADSC) are active.

• Supports 133MHz bus operations, 3.3V core power supply
• 2.5V or 3.3V I/O power supply
• Fast clock-to-output times is 6.5 ns
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write, asynchronous output enable
• IEEE 1149.1 JTAG-compatible boundary scan
• On-chip error correction code (ECC) to reduce soft error rate (SER)
• 100-pin TQFP package, industrial ambient temperature range from -40°C to +85°C

Warnings

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.