MT48LC2M32B2B5-6A IT:J is a SDR SDRAM. It uses a 64Mb SDRAM and a high-speed CMOS, dynamic random-access memory containing 67,108,864 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4's 67,108,864-bit banks are organized as 8192 rows by 2048 columns by 4 bits. Each of the 16,777,216-bit banks are organized as 2048 rows by 256 columns by 32bits. It supports CAS latency (CL) of 1, 2, and 3.
- Operating supply voltage range is 3V to 3.6V (VDD, VDDQ)
- 2Meg x 32 configuration (512K x 32 x 4 banks), PC100-compliant
- Packaging style is 90-ball VFBGA (8mm x 13mm)
- Clock frequency is 167MHz, auto refresh
- Industrial temperature range is -40�C to +85�C
- Fully synchronous to all signals registered on positive edge of system clock
- Internal pipelined operation; column address can be changed every clock cycle
- Internal banks for hiding row access/precharge
- Auto precharge, includes concurrent auto precharge and auto refresh modes
- LVTTL-compatible inputs and outputs
Other details
| Brand |
MICRON |
| Part Number |
MT48LC2M32B2B5-6A ITJ |
| Quantity |
Each |
| Technical Data Sheet EN |
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