MT47H128M16RT-25E AIT:C is an DDR2 SDRAM. It uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially for 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access for the DDR2 SDRAM effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bitwide, one-half-clock-cycle data transfers at the I/O balls.
- Operating voltage range is 1.0V to 2.3V (VSS)
- 128Meg x 16 configuration, AEC-Q100- qualified
- Packaging style is 84-ball 9mm x 12.5mm FBGA
- Timing (cycle time) is 2.5ns at CL = 5 (DDR2-800)
- Posted CAS additive latency (AL)
- Data rate is 800MT/s, differential data strobe (DQS, DQS#) option
- DLL to align DQ and DQS transitions with CK, duplicate output strobe (RDQS) option for x8
- Programmable CAS latency (CL)
- On-die termination (ODT), supports JEDEC clock jitter specification
- JEDEC-standard 1.8V I/O (SSTL
- 18-compatible), 8D response time
Other details
| Brand |
MICRON |
| Part Number |
MT47H128M16RT-25E AITC |
| Quantity |
Each |
| Technical Data Sheet EN |
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