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Description
The MachXO series Complex Programmable Logic Device (CPLD) with low capacity FPGAs, features glue logic, bus bridging, bus interfacing, power-up control and control logic. These devices bring together the best features of CPLD and FPGA devices on a single chip. The devices use look-up tables (LUTs) and embedded block memories traditionally associated with FPGAs for flexible and efficient logic implementation. Through non-volatile technology, the devices provide the single-chip, high-security, instant-ON capabilities traditionally associated with CPLDs. Finally, advanced process technology and careful design will provide the high pin-to-pin performance also associated with CPLDs. The ispLEVER® design tools from Lattice allow complex designs to be efficiently implemented using the MachXO family of devices. Popular logic synthesis tools provide synthesis library support for MachXO.
- Non-volatile, infinitely reconfigurable
- Sleep mode
- TransFR� reconfiguration (TFR)
- High I/O to logic density
- Embedded and distributed memory
- Flexible I/O buffer
- sysCLOCK� PLLs
- System level support
Industrial
Warnings Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.Other details
Brand | LATTICE SEMICONDUCTOR |
Part Number | LCMXO640C-3TN100C |
Quantity | Each |
Technical Data Sheet EN |
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Bulk Discount
Quantity | Price |
2 | ₹ 1957.81 |
3-5 | ₹ 1937.84 |
5-10 | ₹ 1897.88 |
10+ | ₹ 1857.93 |
Bulk discount will be automatically applied during checkout based on quantity.