IS43LD16640D-18BLI is a mobile 64Mb x 16 1Gbit CMOS LPDDR2 DRAM. The device is organized as 8 banks of 8Meg words of 16bits or 4Meg words of 32bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 4n bits are prefetched to achieve very high bandwidth.
- Low-voltage core and I/O power supplies VDD2 = 1.14-1.3V, VDDCA/VDDQ = 1.14-1.3V, VDD1 = 1.7-1.95V
- High speed un-terminated logic (HSUL-12) I/O interface
- Four-bit pre-fetch DDR architecture, eight internal banks for concurrent operation
- Multiplexed, double data rate, command/address inputs
- Bidirectional/differential data strobe per byte of data (DQS/DQS#)
- Programmable read/write latencies (RL/WL) and burst lengths (4,8 or 16)
- ZQ calibration, on-chip temperature sensor to control self-refresh rate
- Partial -array self refresh (PASR), deep power-down mode (DPD)
- 533MHz clock frequency
- 134 ball BGA package, industrial temperature rating range from -40°C to +85°C
Other details
| Brand |
INTEGRATED SILICON SOLUTION (ISSI) |
| Part Number |
IS43LD16640D-18BLI |
| Quantity |
Each |
| Technical Data Sheet EN |
 |
All product and company names are trademarks™ or registered® trademarks of their respective holders. Use of them does not imply any affiliation with or endorsement by them. Image is for illustrative purposes only. Please refer to product description.
