ALLIANCE MEMORY AS4C32M16D2A-25BCN DRAM, DDR2, 512 Mbit, 32M x 16bit, 400 MHz, FBGA, 84 Pins

AS4C32M16D2A-25BCN is a 32M x 16bit DDR2 synchronous DRAM (SDRAM). It is a high-speed CMOS double-data-rate-two (DDR2), synchronous dynamic random-access memory (SDRAM) containing 512Mbits in a 16-bit wide data I/Os. It is internally configured as a quad bank DRAM, 4 banks x 8Mb addresses x 16 I/Os. The device is designed to comply with DDR2 DRAM key features such as posted CAS# with additive latency, write latency = read latency -1, off-chip driver (OCD) impedance adjustment, and on die termination(ODT). All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS#) in a source synchronous fashion. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence.

• JEDEC standard compliant, JEDEC standard 1.8V I/O (SSTL-18-compatible)
• Power supplies: VDD and VDDQ = +1.8V ± 0.1V, 8192 refresh cycles / 64ms, FBGA package
• Supports JEDEC clock jitter specification, fully synchronous operation
• Differential clock, CK and CK#, bidirectional single/differential data strobe, DQS and DQS#
• 4 internal banks for concurrent operation, 4bit prefetch architecture
• Precharge and active power down, programmable mode and extended mode registers
• Posted CAS# additive latency (AL): 0, 1, 2, 3, 4, 5, 6, WRITE latency = READ latency - 1 tCK
• Burst lengths: 4 or 8, burst type: sequential / interleave, DLL enable/disable
• Off-chip driver (OCD), impedance adjustment, adjustable data-output drive strength
• 400MHz clock frequency, 800Mbps/pin data rate, operating temperature: TC = 0 to 95°C