| ₹ 18920.0 includes GST and import duties. | |
| B2B customers can avail ₹ 2885.3 ITC on this product | |
| 100% Secure Payments | 100% Genuine product | |
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Description
The Alchitry Au V2 features an Artix 7 FPGA and is the gold standard for FPGA development boards. It's possibly one of the strongest boards of its type on the market.
Features & Specs
- XC7A35T-2FTG256I FPGA (speed and temperature grade upgrade over Au V1)
- 104 IO pins broken out across two headers
- 22 are triple voltage (3.3V, 2.5V, or 1.8V) of which 20 are LVDS_25 capable outputs
- 44 pins are routed as 100 ohm differential pairs (includes 20 dual voltage pins)
- Remaining IO routed as 50 ohm single ended (~90 ohm when used as diff pairs)
- 2 1.35V pins on bank B
- 8 pairs can be used as inputs to the XADC (0-1V input range)
- Remaining IO is at 3.3V
- All pairs can be used as LVDS_25 inputs except three pairs on bank B
- Control Header
- 8 IO pins also connected to on-board LEDs
- 1 IO pin also connected to on-board reset button
- JTAG
- Analog voltages and dedicated XADC input (0-1V range)
- Raw power input/3.3V regulated output
- QWIIC connector (shares pins on bank B)
- 100MHz oscillator
- 8 general purpose LEDs
- 1 button (typically used as reset)
- 256MB DDR3L @ 800Mb/s (400MHz)
- 32MBit Configuration FLASH
- FT2232HQ USB -> JTAG and USB -> UART (12Mbaud max)
- 5-12V input voltage on-board power supply
- 3.3V @ 4A (IO)
- 2.5V @ 500mA (tiple voltage pins, derived from 3.3V)
- 1V @ 4A (VCCINT)
- 1.8V @ 1.2A (VCCAUX, triple voltage pins)
- 1.35V @1.2A (DDR3L)
- 1.8V @ 200mA (analog)
Features & Specs
- XC7A35T-2FTG256I FPGA (speed and temperature grade upgrade over Au V1)
- 104 IO pins broken out across two headers
- 22 are triple voltage (3.3V, 2.5V, or 1.8V) of which 20 are LVDS_25 capable outputs
- 44 pins are routed as 100 ohm differential pairs (includes 20 dual voltage pins)
- Remaining IO routed as 50 ohm single ended (~90 ohm when used as diff pairs)
- 2 1.35V pins on bank B
- 8 pairs can be used as inputs to the XADC (0-1V input range)
- Remaining IO is at 3.3V
- All pairs can be used as LVDS_25 inputs except three pairs on bank B
- Control Header
- 8 IO pins also connected to on-board LEDs
- 1 IO pin also connected to on-board reset button
- JTAG
- Analog voltages and dedicated XADC input (0-1V range)
- Raw power input/3.3V regulated output
- QWIIC connector (shares pins on bank B)
- 100MHz oscillator
- 8 general purpose LEDs
- 1 button (typically used as reset)
- 256MB DDR3L @ 800Mb/s (400MHz)
- 32MBit Configuration FLASH
- FT2232HQ USB -> JTAG and USB -> UART (12Mbaud max)
- 5-12V input voltage on-board power supply
- 3.3V @ 4A (IO)
- 2.5V @ 500mA (tiple voltage pins, derived from 3.3V)
- 1V @ 4A (VCCINT)
- 1.8V @ 1.2A (VCCAUX, triple voltage pins)
- 1.35V @1.2A (DDR3L)
- 1.8V @ 200mA (analog)
Documentation
- Schematic
- Drawing
- Pinout and Trace Lengths
- 3D Model (STEP)
- Simplified 3D Model (STEP)
- DC and AC Switching Characteristics (DS181)
- SelectIO Resources (UG471)
- Clocking Resources (UG472)
- All Xilinx Artix 7 Docs
WARNING: This product may contain chemicals known to the State of California to cause cancer and birth defects or other reproductive harm. See link below for more information. www.P65Warnings.ca.gov
Bulk Discount
| Quantity | Price |
| 2 | ₹ 18541.6 |
| 3-5 | ₹ 18352.4 |
| 5-10 | ₹ 17974.0 |
| 10+ | ₹ 17595.6 |
Bulk discount will be automatically applied during checkout based on quantity.