INFINEON CY7C1051H30-10ZSXI SRAM, Asynchronous SRAM, 8 Mbit, 512K x 16bit, TSOP, 44 Pins, 2.2 V

CY7C1051H30-10ZSXI is a high-performance CMOS fast static RAM device with embedded ECC. To access the device, assert the chip enable (active low CE) input LOW. To perform data writes, assert the Write Enable (active low WE) input LOW, and provide the data and address on the device data pins (I/O0 through I/O15) and address pins (A0 through A18) respectively. The Byte High Enable (active low BHE) and Byte Low Enable (active low BLE) inputs control byte writes, and write data on the corresponding I/O lines to the memory location specified. BHE controls I/O8 through I/O15 and BLE controls I/O0 through I/O7. To perform data reads, assert the Output Enable (active low OE) input and provide the required address on the address lines. Read data is accessible on I/O lines (I/O0 through I/O15). It can perform byte accesses by asserting the required byte enable signal (active low BHE or active low BLE) to read either the upper byte or the lower byte of data from the specified address location.

• Embedded error-correcting code (ECC) for single-bit error correction
• Transistor-transistor logic (TTL) compatible inputs and outputs
• Operating voltage range from 2.2V to 3.6V
• Input leakage current range from -1.0 to +1.0µA (GND < VIN < VCC)
• Operating supply current is 90.0mA typ (VCC = Max, IOUT = 0mA, f = 100MHz)
• Input capacitance is 10pF (TA = 25°C, f = 1MHz, VCC = VCC(typ))
• I/O capacitance is 10pF (TA = 25°C, f = 1MHz, VCC = VCC(typ))
• VCC for data retention is 1.0V minimum
• Operation recovery time is 10.0ns minimum (VCC > 2.2V)
• 44-pin TSOP II package, industrial temperature range from -40 to 85°C