ALLIANCE MEMORY AS4C32M16D2A-25BIN DRAM, DDR2, 512 Mbit, 32M x 16bit, 400 MHz, FBGA, 84 Pins

AS4C32M16D2A-25BIN is a 32M x 16bit DDR2 synchronous dynamic random-access memory DRAM (SDRAM). It is a high-speed CMOS double-data-rate two (DDR2) SDRAM containing 512Mbits in a 16bit wide data I/Os. It is internally configured as a quad bank DRAM, 4 banks x 8Mb addresses x 16 I/Os. The device is designed to comply with DDR2 DRAM key features such as posted CAS# with additive latency, write latency=read latency -1, off-chip driver (OCD) impedance adjustment, and on-die termination (ODT). All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). Accesses begin with the registration of a bank activate command, and then it is followed by a read or write command. Read and write accesses to the DDR2 SDRAM are 4 or 8-bit burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.

• JEDEC standard compliant, JEDEC standard 1.8V I/O (SSTL-18-compatible)
• Power supplies: VDD and VDDQ = +1.8V ±0.1V, supports JEDEC clock jitter specification
• Fully synchronous operation, differential clock, CK and CK#, 4-bit prefetch architecture
• Bidirectional single/differential data strobe, DQS and DQS#, internal pipeline architecture
• 4 internal banks for concurrent operation, precharge and active power down
• Programmable mode and extended mode registers, posted CAS# additive latency (AL) 0, 1, 2, 3, 4, 5, 6
• WRITE latency = READ latency - 1 tCK, burst lengths: 4 or 8
• Off-chip driver (OCD), impedance adjustment, adjustable data-output drive strength
• On-die termination (ODT), 8192 refresh cycles / 64ms, 400MHz clock frequency
• 800Mbps/pin data rate, FBGA package, operating temperature range (TC) from -40°C to 95°C