ON SEMICONDUCTOR MC100LVEL14DWG Clock Buffer, 1 GHz, 3V-3.8V supply, 5 Outputs, SOIC-32

The MC100LVEL14DWG is a 1:5 low skew Clock Distribution Chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or if positive power supplies are used, PECL input signal. The LVEL14 is functionally and pin compatible with the EL14 but is designed to operate in ECL or PECL mode. The LVEL14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When low (or left open and pulled LOW by the input pull-down resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the low state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control.