{"product_id":"alchitry-pt-v2","title":"Alchitry Pt V2","description":"\u003cp\u003eExperience platinum-tier performance with the Alchitry Pt V2, an FPGA board optimized for high-speed communication in a minimal footprint featuring the Xilinx Artix-7.\u003c\/p\u003e\n\u003cdiv\u003e \n \u003ch2\u003eFeatures \u0026amp; Specs\u003c\/h2\u003e \n \u003cp\u003e\u003c\/p\u003e \n \u003cdiv\u003e \n  \u003cdiv\u003e \n   \u003cdiv\u003e \n    \u003cul\u003e \n     \u003cli\u003eXC7A100T-2FGG84I FPGA\u003c\/li\u003e \n     \u003cli\u003eConnectors on both sides of the board allow two independent stacks (IO isn't shared)\u003c\/li\u003e \n     \u003cli\u003e206 IO pins \n      \u003cul\u003e \n       \u003cli\u003eAll IO pairs are LVDS_25 capable inputs or TMDS_33 capable IO\u003c\/li\u003e \n       \u003cli\u003e112 on the top \n        \u003cul\u003e \n         \u003cli\u003e32 triple voltage (3.3V, 2.5V, or 1.8V) pins (16 pairs) capable of LVDS_25 IO\u003c\/li\u003e \n         \u003cli\u003e76 routed as 100 ohm differential pairs\u003c\/li\u003e \n         \u003cli\u003eRemaining IO routed as 50 ohm single ended\u003c\/li\u003e \n         \u003cli\u003e8 are on the control header\u003c\/li\u003e \n        \u003c\/ul\u003e \u003c\/li\u003e \n       \u003cli\u003e92 on the bottom \n        \u003cul\u003e \n         \u003cli\u003e24 routed as 100 ohm differential pairs\u003c\/li\u003e \n         \u003cli\u003eRemaining IO routed as 50 ohm single ended\u003c\/li\u003e \n         \u003cli\u003e8 are on the control header\u003c\/li\u003e \n        \u003c\/ul\u003e \u003c\/li\u003e \n       \u003cli\u003e2 on QWIIC connector\u003c\/li\u003e \n      \u003c\/ul\u003e \u003c\/li\u003e \n     \u003cli\u003e20 GTP pins broken out on the bottom \n      \u003cul\u003e \n       \u003cli\u003e2 clock input pairs\u003c\/li\u003e \n       \u003cli\u003e4 Tx pairs\u003c\/li\u003e \n       \u003cli\u003e4 Rx pairs\u003c\/li\u003e \n       \u003cli\u003e6.25 Gb\/s bandwidth per pair\u003c\/li\u003e \n      \u003c\/ul\u003e \u003c\/li\u003e \n     \u003cli\u003e100MHz oscillator\u003c\/li\u003e \n     \u003cli\u003e8 general purpose LEDs\u003c\/li\u003e \n     \u003cli\u003e1 button (typically used as reset)\u003c\/li\u003e \n     \u003cli\u003e256MB DDR3L @ 800Mb\/s (400MHz)\u003c\/li\u003e \n     \u003cli\u003e32MBit Configuration FLASH\u003c\/li\u003e \n     \u003cli\u003eFT2232HQ USB -\u0026gt; JTAG and USB -\u0026gt; UART (12Mbaud max) or FIFO (~8MB\/s)\u003c\/li\u003e \n     \u003cli\u003e5-12V input voltage on-board power supply \n      \u003cul\u003e \n       \u003cli\u003e3.3V @ 4A (IO)\u003c\/li\u003e \n       \u003cli\u003e2.5V @ 500mA (triple voltage pins, derived from 3.3V)\u003c\/li\u003e \n       \u003cli\u003e1V @ 4A (VCCINT)\u003c\/li\u003e \n       \u003cli\u003e1.8V @ 1.2A (VCCAUX, triple voltage pins)\u003c\/li\u003e \n       \u003cli\u003e1.35V @1.2A (DDR3L)\u003c\/li\u003e \n       \u003cli\u003e1.8V @ 200mA (analog)\u003c\/li\u003e \n       \u003cli\u003e1V @ 1.5A (MGTAVCC, derived from 3.3V)\u003c\/li\u003e \n       \u003cli\u003e1.2V @1.5A (MGTAVTT, derived from 3.3V)\u003c\/li\u003e \n      \u003c\/ul\u003e \u003c\/li\u003e \n    \u003c\/ul\u003e \n   \u003c\/div\u003e \n  \u003c\/div\u003e \n \u003c\/div\u003e \n \u003cp\u003e\u003c\/p\u003e \n\u003c\/div\u003e\n\u003cdiv\u003e \n \u003ch2\u003eFeatures \u0026amp; Specs\u003c\/h2\u003e \n \u003cp\u003e\u003c\/p\u003e \n \u003cdiv\u003e \n  \u003cdiv\u003e \n   \u003cdiv\u003e \n    \u003cul\u003e \n     \u003cli\u003eXC7A100T-2FGG84I FPGA\u003c\/li\u003e \n     \u003cli\u003eConnectors on both sides of the board allow two independent stacks (IO isn't shared)\u003c\/li\u003e \n     \u003cli\u003e206 IO pins \n      \u003cul\u003e \n       \u003cli\u003eAll IO pairs are LVDS_25 capable inputs or TMDS_33 capable IO\u003c\/li\u003e \n       \u003cli\u003e112 on the top \n        \u003cul\u003e \n         \u003cli\u003e32 triple voltage (3.3V, 2.5V, or 1.8V) pins (16 pairs) capable of LVDS_25 IO\u003c\/li\u003e \n         \u003cli\u003e76 routed as 100 ohm differential pairs\u003c\/li\u003e \n         \u003cli\u003eRemaining IO routed as 50 ohm single ended\u003c\/li\u003e \n         \u003cli\u003e8 are on the control header\u003c\/li\u003e \n        \u003c\/ul\u003e \u003c\/li\u003e \n       \u003cli\u003e92 on the bottom \n        \u003cul\u003e \n         \u003cli\u003e24 routed as 100 ohm differential pairs\u003c\/li\u003e \n         \u003cli\u003eRemaining IO routed as 50 ohm single ended\u003c\/li\u003e \n         \u003cli\u003e8 are on the control header\u003c\/li\u003e \n        \u003c\/ul\u003e \u003c\/li\u003e \n       \u003cli\u003e2 on QWIIC connector\u003c\/li\u003e \n      \u003c\/ul\u003e \u003c\/li\u003e \n     \u003cli\u003e20 GTP pins broken out on the bottom \n      \u003cul\u003e \n       \u003cli\u003e2 clock input pairs\u003c\/li\u003e \n       \u003cli\u003e4 Tx pairs\u003c\/li\u003e \n       \u003cli\u003e4 Rx pairs\u003c\/li\u003e \n       \u003cli\u003e6.25 Gb\/s bandwidth per pair\u003c\/li\u003e \n      \u003c\/ul\u003e \u003c\/li\u003e \n     \u003cli\u003e100MHz oscillator\u003c\/li\u003e \n     \u003cli\u003e8 general purpose LEDs\u003c\/li\u003e \n     \u003cli\u003e1 button (typically used as reset)\u003c\/li\u003e \n     \u003cli\u003e256MB DDR3L @ 800Mb\/s (400MHz)\u003c\/li\u003e \n     \u003cli\u003e32MBit Configuration FLASH\u003c\/li\u003e \n     \u003cli\u003eFT2232HQ USB -\u0026gt; JTAG and USB -\u0026gt; UART (12Mbaud max) or FIFO (~8MB\/s)\u003c\/li\u003e \n     \u003cli\u003e5-12V input voltage on-board power supply \n      \u003cul\u003e \n       \u003cli\u003e3.3V @ 4A (IO)\u003c\/li\u003e \n       \u003cli\u003e2.5V @ 500mA (triple voltage pins, derived from 3.3V)\u003c\/li\u003e \n       \u003cli\u003e1V @ 4A (VCCINT)\u003c\/li\u003e \n       \u003cli\u003e1.8V @ 1.2A (VCCAUX, triple voltage pins)\u003c\/li\u003e \n       \u003cli\u003e1.35V @1.2A (DDR3L)\u003c\/li\u003e \n       \u003cli\u003e1.8V @ 200mA (analog)\u003c\/li\u003e \n       \u003cli\u003e1V @ 1.5A (MGTAVCC, derived from 3.3V)\u003c\/li\u003e \n       \u003cli\u003e1.2V @1.5A (MGTAVTT, derived from 3.3V)\u003c\/li\u003e \n      \u003c\/ul\u003e \u003c\/li\u003e \n    \u003c\/ul\u003e \n   \u003c\/div\u003e \n  \u003c\/div\u003e \n \u003c\/div\u003e \n \u003cp\u003e\u003c\/p\u003e \n\u003c\/div\u003e\n\u003ch2\u003eDocumentation\u003c\/h2\u003e \n\u003cp\u003e\u003c\/p\u003e \n\u003cul\u003e \n \u003cli\u003e\u003ca href=\"https:\/\/cdn.alchitry.com\/docs\/Pt-V2\/Alchitry%20Platinum%20Rev%20A.pdf\" target=\"_blank\" rel=\"noopener\"\u003eSchematic\u003c\/a\u003e\u003c\/li\u003e \n \u003cli\u003e\u003ca href=\"https:\/\/cdn.alchitry.com\/docs\/Pt-V2\/Alchitry%20Platinum%20v2.step\" target=\"_blank\" rel=\"noopener\"\u003e3D Model (STEP)\u003c\/a\u003e\u003c\/li\u003e \n \u003cli\u003e\u003ca href=\"https:\/\/docs.amd.com\/v\/u\/en-US\/ds181_Artix_7_Data_Sheet\" target=\"_blank\" rel=\"noopener\"\u003eDC and AC Switching Characteristics (DS181)\u003c\/a\u003e\u003c\/li\u003e \n \u003cli\u003e\u003ca href=\"https:\/\/docs.amd.com\/v\/u\/en-US\/ug471_7Series_SelectIO\" target=\"_blank\" rel=\"noopener\"\u003eSelectIO Resources (UG471)\u003c\/a\u003e\u003c\/li\u003e \n \u003cli\u003e\u003ca href=\"https:\/\/docs.amd.com\/v\/u\/en-US\/ug472_7Series_Clocking\" target=\"_blank\" rel=\"noopener\"\u003eClocking Resources (UG472)\u003c\/a\u003e\u003c\/li\u003e \n \u003cli\u003e\u003ca href=\"https:\/\/docs.amd.com\/search\/documents?filters=Product_custom~%2522Adaptive+SoCs+%2526+FPGAs%257CFPGA%257CArtix+7%2522\u0026amp;content-lang=en-US\" target=\"_blank\" rel=\"noopener\"\u003eAll Xilinx Artix 7 Docs\u003c\/a\u003e\u003c\/li\u003e \n\u003c\/ul\u003e \n\u003cp\u003eThe Artix 7 FPGA requires a free license for Vivado. \u003ca href=\"https:\/\/alchitry.com\/tutorials\/setup\/vivado\/\" target=\"_blank\" rel=\"noopener\"\u003eClick here\u003c\/a\u003e for instructions on installing it.\u003c\/p\u003e \n\u003cp\u003e\u003c\/p\u003e \n\u003cdiv\u003e \n \u003cdiv\u003e \n  \u003cdiv\u003e \n   \u003cdiv\u003e \n    \u003cdiv\u003e \n     \u003cdiv\u003e \n      \u003cdiv\u003e \n       \u003cp\u003e\u003c\/p\u003e \n       \u003cdiv\u003e \n        \u003cspan\u003e \u003cb\u003eWARNING:\u003c\/b\u003e This product may contain chemicals known to the State of California to cause cancer and birth defects or other reproductive harm. See link below for more information. \u003ca href=\"https:\/\/www.P65Warnings.ca.gov\"\u003ewww.P65Warnings.ca.gov\u003c\/a\u003e \u003c\/span\u003e \n       \u003c\/div\u003e \n      \u003c\/div\u003e \n     \u003c\/div\u003e \n     \u003cdiv\u003e\u003c\/div\u003e \n    \u003c\/div\u003e \n   \u003c\/div\u003e \n  \u003c\/div\u003e \n \u003c\/div\u003e \n\u003c\/div\u003e","brand":"sparkfun-10","offers":[{"title":"Default Title","offer_id":42643899678805,"sku":"27873:DEV-27873:spark","price":41280.0,"currency_code":"INR","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/1034\/1611\/files\/27873-Alchitry-Pt-V2-Feature.jpg?v=1782359894","url":"https:\/\/www.tanotis.com\/products\/alchitry-pt-v2","provider":"Tanotis","version":"1.0","type":"link"}