{"product_id":"alchitry-au-v2","title":"Alchitry Au V2","description":"\u003cp\u003eThe Alchitry Au V2 features an Artix 7 FPGA and is the gold standard for FPGA development boards. It's possibly one of the strongest boards of its type on the market.\u003c\/p\u003e\n\u003cdiv\u003e \n \u003ch2\u003eFeatures \u0026amp; Specs\u003c\/h2\u003e \n \u003cp\u003e\u003c\/p\u003e \n \u003cdiv\u003e \n  \u003cdiv\u003e \n   \u003cdiv\u003e \n    \u003cul\u003e \n     \u003cli\u003eXC7A35T-2FTG256I FPGA (speed and temperature grade upgrade over Au V1)\u003c\/li\u003e \n     \u003cli\u003e104 IO pins broken out across two headers \n      \u003cul\u003e \n       \u003cli\u003e22 are triple voltage (3.3V, 2.5V, or 1.8V) of which 20 are LVDS_25 capable outputs\u003c\/li\u003e \n       \u003cli\u003e44 pins are routed as 100 ohm differential pairs (includes 20 dual voltage pins)\u003c\/li\u003e \n       \u003cli\u003eRemaining IO routed as 50 ohm single ended (~90 ohm when used as diff pairs)\u003c\/li\u003e \n       \u003cli\u003e2 1.35V pins on bank B\u003c\/li\u003e \n       \u003cli\u003e8 pairs can be used as inputs to the XADC (0-1V input range)\u003c\/li\u003e \n       \u003cli\u003eRemaining IO is at 3.3V\u003c\/li\u003e \n       \u003cli\u003eAll pairs can be used as LVDS_25 inputs except three pairs on bank B\u003c\/li\u003e \n      \u003c\/ul\u003e \u003c\/li\u003e \n     \u003cli\u003eControl Header \n      \u003cul\u003e \n       \u003cli\u003e8 IO pins also connected to on-board LEDs\u003c\/li\u003e \n       \u003cli\u003e1 IO pin also connected to on-board reset button\u003c\/li\u003e \n       \u003cli\u003eJTAG\u003c\/li\u003e \n       \u003cli\u003eAnalog voltages and dedicated XADC input (0-1V range)\u003c\/li\u003e \n       \u003cli\u003eRaw power input\/3.3V regulated output\u003c\/li\u003e \n      \u003c\/ul\u003e \u003c\/li\u003e \n     \u003cli\u003eQWIIC connector (shares pins on bank B)\u003c\/li\u003e \n     \u003cli\u003e100MHz oscillator\u003c\/li\u003e \n     \u003cli\u003e8 general purpose LEDs\u003c\/li\u003e \n     \u003cli\u003e1 button (typically used as reset)\u003c\/li\u003e \n     \u003cli\u003e256MB DDR3L @ 800Mb\/s (400MHz)\u003c\/li\u003e \n     \u003cli\u003e32MBit Configuration FLASH\u003c\/li\u003e \n     \u003cli\u003eFT2232HQ USB -\u0026gt; JTAG and USB -\u0026gt; UART (12Mbaud max)\u003c\/li\u003e \n     \u003cli\u003e5-12V input voltage on-board power supply \n      \u003cul\u003e \n       \u003cli\u003e3.3V @ 4A (IO)\u003c\/li\u003e \n       \u003cli\u003e2.5V @ 500mA (tiple voltage pins, derived from 3.3V)\u003c\/li\u003e \n       \u003cli\u003e1V @ 4A (VCCINT)\u003c\/li\u003e \n       \u003cli\u003e1.8V @ 1.2A (VCCAUX, triple voltage pins)\u003c\/li\u003e \n       \u003cli\u003e1.35V @1.2A (DDR3L)\u003c\/li\u003e \n       \u003cli\u003e1.8V @ 200mA (analog)\u003c\/li\u003e \n      \u003c\/ul\u003e \u003c\/li\u003e \n    \u003c\/ul\u003e \n   \u003c\/div\u003e \n  \u003c\/div\u003e \n \u003c\/div\u003e \n \u003cp\u003e\u003c\/p\u003e \n\u003c\/div\u003e\n\u003cdiv\u003e \n \u003ch2\u003eFeatures \u0026amp; Specs\u003c\/h2\u003e \n \u003cp\u003e\u003c\/p\u003e \n \u003cdiv\u003e \n  \u003cdiv\u003e \n   \u003cdiv\u003e \n    \u003cul\u003e \n     \u003cli\u003eXC7A35T-2FTG256I FPGA (speed and temperature grade upgrade over Au V1)\u003c\/li\u003e \n     \u003cli\u003e104 IO pins broken out across two headers \n      \u003cul\u003e \n       \u003cli\u003e22 are triple voltage (3.3V, 2.5V, or 1.8V) of which 20 are LVDS_25 capable outputs\u003c\/li\u003e \n       \u003cli\u003e44 pins are routed as 100 ohm differential pairs (includes 20 dual voltage pins)\u003c\/li\u003e \n       \u003cli\u003eRemaining IO routed as 50 ohm single ended (~90 ohm when used as diff pairs)\u003c\/li\u003e \n       \u003cli\u003e2 1.35V pins on bank B\u003c\/li\u003e \n       \u003cli\u003e8 pairs can be used as inputs to the XADC (0-1V input range)\u003c\/li\u003e \n       \u003cli\u003eRemaining IO is at 3.3V\u003c\/li\u003e \n       \u003cli\u003eAll pairs can be used as LVDS_25 inputs except three pairs on bank B\u003c\/li\u003e \n      \u003c\/ul\u003e \u003c\/li\u003e \n     \u003cli\u003eControl Header \n      \u003cul\u003e \n       \u003cli\u003e8 IO pins also connected to on-board LEDs\u003c\/li\u003e \n       \u003cli\u003e1 IO pin also connected to on-board reset button\u003c\/li\u003e \n       \u003cli\u003eJTAG\u003c\/li\u003e \n       \u003cli\u003eAnalog voltages and dedicated XADC input (0-1V range)\u003c\/li\u003e \n       \u003cli\u003eRaw power input\/3.3V regulated output\u003c\/li\u003e \n      \u003c\/ul\u003e \u003c\/li\u003e \n     \u003cli\u003eQWIIC connector (shares pins on bank B)\u003c\/li\u003e \n     \u003cli\u003e100MHz oscillator\u003c\/li\u003e \n     \u003cli\u003e8 general purpose LEDs\u003c\/li\u003e \n     \u003cli\u003e1 button (typically used as reset)\u003c\/li\u003e \n     \u003cli\u003e256MB DDR3L @ 800Mb\/s (400MHz)\u003c\/li\u003e \n     \u003cli\u003e32MBit Configuration FLASH\u003c\/li\u003e \n     \u003cli\u003eFT2232HQ USB -\u0026gt; JTAG and USB -\u0026gt; UART (12Mbaud max)\u003c\/li\u003e \n     \u003cli\u003e5-12V input voltage on-board power supply \n      \u003cul\u003e \n       \u003cli\u003e3.3V @ 4A (IO)\u003c\/li\u003e \n       \u003cli\u003e2.5V @ 500mA (tiple voltage pins, derived from 3.3V)\u003c\/li\u003e \n       \u003cli\u003e1V @ 4A (VCCINT)\u003c\/li\u003e \n       \u003cli\u003e1.8V @ 1.2A (VCCAUX, triple voltage pins)\u003c\/li\u003e \n       \u003cli\u003e1.35V @1.2A (DDR3L)\u003c\/li\u003e \n       \u003cli\u003e1.8V @ 200mA (analog)\u003c\/li\u003e \n      \u003c\/ul\u003e \u003c\/li\u003e \n    \u003c\/ul\u003e \n   \u003c\/div\u003e \n  \u003c\/div\u003e \n \u003c\/div\u003e \n \u003cp\u003e\u003c\/p\u003e \n\u003c\/div\u003e\n\u003ch2\u003eDocumentation\u003c\/h2\u003e \n\u003cp\u003e\u003c\/p\u003e \n\u003cul\u003e \n \u003cli\u003e\u003ca href=\"https:\/\/cdn.sparkfun.com\/assets\/2\/2\/e\/2\/1\/AuSchematic.pdf\" target=\"_blank\" rel=\"noopener\"\u003eSchematic\u003c\/a\u003e\u003c\/li\u003e \n \u003cli\u003e\u003ca href=\"https:\/\/cdn.sparkfun.com\/assets\/3\/7\/6\/b\/9\/AuDrawing.pdf\" target=\"_blank\" rel=\"noopener\"\u003eDrawing\u003c\/a\u003e\u003c\/li\u003e \n \u003cli\u003e\u003ca href=\"https:\/\/docs.google.com\/spreadsheets\/d\/1WxeS5YJ1MgcgeiRLXJ_PuZC4l7f2cVPHpaNJcFdKyg8\/edit?usp=sharing\" target=\"_blank\" rel=\"noopener\"\u003ePinout and Trace Lengths\u003c\/a\u003e\u003c\/li\u003e \n \u003cli\u003e\u003ca href=\"https:\/\/cdn.alchitry.com\/docs\/Au-V2\/Au.step\" target=\"_blank\" rel=\"noopener noreferrer\"\u003e3D Model (STEP)\u003c\/a\u003e\u003c\/li\u003e \n \u003cli\u003e\u003ca href=\"https:\/\/cdn.alchitry.com\/docs\/Au-V2\/AuSimple.step\" target=\"_blank\" rel=\"noopener noreferrer\"\u003eSimplified 3D Model (STEP)\u003c\/a\u003e\u003c\/li\u003e \n \u003cli\u003e\u003ca href=\"https:\/\/docs.amd.com\/v\/u\/en-US\/ds181_Artix_7_Data_Sheet\" target=\"_blank\" rel=\"noopener noreferrer\"\u003eDC and AC Switching Characteristics (DS181)\u003c\/a\u003e\u003c\/li\u003e \n \u003cli\u003e\u003ca href=\"https:\/\/docs.amd.com\/v\/u\/en-US\/ug471_7Series_SelectIO\" target=\"_blank\" rel=\"noopener noreferrer\"\u003eSelectIO Resources (UG471)\u003c\/a\u003e\u003c\/li\u003e \n \u003cli\u003e\u003ca href=\"https:\/\/docs.amd.com\/v\/u\/en-US\/ug472_7Series_Clocking\" target=\"_blank\" rel=\"noopener noreferrer\"\u003eClocking Resources (UG472)\u003c\/a\u003e\u003c\/li\u003e \n \u003cli\u003e\u003ca href=\"https:\/\/docs.amd.com\/search\/documents?filters=Product_custom~%2522Adaptive+SoCs+%2526+FPGAs%257CFPGA%257CArtix+7%2522\u0026amp;content-lang=en-US\" target=\"_blank\" rel=\"noopener noreferrer\"\u003eAll Xilinx Artix 7 Docs\u003c\/a\u003e\u003c\/li\u003e \n\u003c\/ul\u003e \n\u003cp\u003e\u003c\/p\u003e \n\u003cdiv\u003e \n \u003cdiv\u003e \n  \u003cdiv\u003e \n   \u003cdiv\u003e \n    \u003cdiv\u003e \n     \u003cdiv\u003e \n      \u003cdiv\u003e \n       \u003cp\u003e\u003c\/p\u003e \n       \u003cdiv\u003e \n        \u003cspan\u003e \u003cb\u003eWARNING:\u003c\/b\u003e This product may contain chemicals known to the State of California to cause cancer and birth defects or other reproductive harm. See link below for more information. \u003ca href=\"https:\/\/www.P65Warnings.ca.gov\"\u003ewww.P65Warnings.ca.gov\u003c\/a\u003e \u003c\/span\u003e \n       \u003c\/div\u003e \n      \u003c\/div\u003e \n     \u003c\/div\u003e \n     \u003cdiv\u003e\u003c\/div\u003e \n    \u003c\/div\u003e \n   \u003c\/div\u003e \n  \u003c\/div\u003e \n \u003c\/div\u003e \n\u003c\/div\u003e","brand":"sparkfun-10","offers":[{"title":"Default Title","offer_id":42643949060181,"sku":"27874:DEV-27874:spark","price":18920.0,"currency_code":"INR","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/1034\/1611\/files\/DEV-27874-Alchitry-Au-V2-Feature.jpg?v=1782360568","url":"https:\/\/www.tanotis.com\/products\/alchitry-au-v2","provider":"Tanotis","version":"1.0","type":"link"}